In a Peripheral Component Interconnect Express (PCIe) system, devices having PCIe ports may transmit a packet by using the PCIe ports. For example, a central processing unit (CPU) is connected to an upstream port (UP) of a PCIe switch by using a PCIe port, and a downstream port (DP) of the PCIe switch is connected to an endpoint (EP) device. When the CPU sends a packet to the EP, first, the CPU sends the packet to the UP of the PCIe switch; next, the UP of the PCIe switch sends the packet to the DP connected to the EP; and next, the DP sends the packet to the EP.
When a link between two PCIe ports becomes faulty, to-be-sent packets are piled up at a PCIe port, that is, packet backpressure occurs. If packet backpressure cannot be detected in a timely manner, instruction timeout occurs in a device for sending a packet. Consequently, the device hangs (hang), and cannot work normally.
An existing packet backpressure detection method is as follows: All to-be-sent packets at a PCIe port are stored in a cache unit. A timer is set for each packet stored in the cache unit, and records storage duration of the packet in the cache unit. When a timer that is set for any packet expires, it is determined that packet backpressure occurs at the PCIe port, and an error packet indicating packet backpressure at the PCIe port is sent to an error processing unit.
However, one device may include multiple PCIe ports, and generally, a large quantity of to-be-sent packets are stored in a cache unit at each PCIe port. In the packet backpressure detection method in the prior art, a large quantity of timer resources are applied for, and an error processing unit receives a large quantity of error processing reports. Consequently, bandwidth within a device is excessively occupied, and resources within the device are wasted.